1. Field of the Invention
The present invention provides a non-volatile memory and a method of programming and erasing, and more particularly, the present invention relates to an electrically erasable programmable read-only memory (EEPROM) and a method of programming and erasing.
2. Description of the Prior Art
An EEPROM device is a kind of non-volatile memory. The structure of EEPROMs is similar to that of erasable programmable read-only memories (EPROMS) since both of them have a floating gate for storing charges and a control gate for controlling data access. In a large number of memory cells, each memory cell comprises a floating gate for storing charges which represent data. After the floating gate of the memory cell is charged, the threshold voltage of the memory cell is lifted, so the charged memory cell will not be in a conductive state during addressing in reading. A state of not conducting is regarded as a “0” state or a “1” state by detecting circuits utilizing a binary system. Uncharged memory cells will be regarded as being in a “1” state or in a “0” state correspondingly. In comparison with an EPROM which is programmed and erased as a whole, EEPROM has the advantage of erasing and programming data bit by bit. Therefore, the EEPROM is a byte addressable device.
Since the flash memory is erased block by block rather than bit by bit, EEPROM is superior to the flash memory in partial data revision when compared with the flash memory product, which is rapidly growing in market. The EEPROM is very suitable to be used in an embedded function, such as an address book in cell phones, because of its byte program/erase feature. In addition, EEPROM products usually have good high reliability performance, which increases applicability in application fields requiring repetitive programming, reading, and erasing.
Please refer to FIG. 1, FIG. 1 is a cross-sectional schematic diagram illustrating a prior art EEPROM device 10. As shown in FIG. 1, the prior art EEPROM device 10 is disposed on a semiconductor wafer 11. The semiconductor wafer 11 comprises a P-type silicon substrate 12. The EEPROM device 10 comprises a memory cell 14. The memory cell 14 comprises a source region 16 and a drain region 18 disposed on a surface of the P-type silicon substrate 12, and a channel region 22 between the source region 16 and the drain region 18. Both the source region 16 and the drain region 18 are N-type heavy doped regions. The memory cell 14 further comprises a tunnel oxide layer 24, a floating gate 26, a dielectric layer 28, and a control gate 32. The tunnel oxide layer 24 is disposed on a top surface 25 of the P-type silicon substrate 12, and the tunnel oxide layer 24 covers the channel region 22. The floating gate 26 is disposed on a surface of the tunnel oxide layer 24. The dielectric layer 28 covers the floating gate 26. The control gate 32 is disposed on a surface of the dielectric layer 28 and the surface of the tunnel oxide layer 24.
The EEPROM device 10 further comprises an N-type select gate transistor 34. The select gate transistor 34 comprises a source region 36, a drain region, and a gate 38. Since the drain region of the N-type select gate transistor 34 is overlapped with the source region 16 of the memory cell 14, it is not specially marked. In addition, the source region 36 of the N-type select gate transistor 34 is electrically connected to a bit line (BL).
When the memory cell 14 is selected to perform a program operation, a high positive potential (such as +12 V) is supplied to the control gate 32. At this time, the N-type select gate transistor 34 is turned on to pass a program potential (such as 2.5 V) supplied to the bit line to the source region 16 of the memory cell 14. In addition, a terminal 42 electrically connected to the P-type silicon substrate 12 is grounded. Since the program potential and the potential of the P-type silicon substrate 12 are obviously lower than the positive potential supplied to the control gate 32, high potential differences exist to produce an electric field that transverses the tunnel oxide layer 24. Therefore, electrons flowing from the source region 16 to the drain region 18 will acquire kinetic energy due to the existence of the electric field, and change their acceleration direction and transverse the tunnel oxide layer 24 by Fowler-Nordheim (FN) tunneling mechanism. The electrons then are injected into the floating gate 26 and are trapped in the floating gate 26 to complete the program operation. The threshold voltage of the N-type memory cell 14 is thus lifted.
When the memory cell 14 is selected to perform an erase operation, a high negative potential (such as −12 V) is supplied to the control gate 32. At this time, the N-type select gate transistor 34 is turned on to pass an erase potential (such as +2.5 V) supplied to the bit line to the source region 16 of the memory cell 14. In addition, the terminal 42 electrically connected to the P-type silicon substrate 12 is grounded. Since the erase potential and the potential of the P-type silicon substrate 12 are obviously higher than the potential supplied to the control gate 32, not only is the channel region 22 of the memory cell 14 not conducted, but also high potential differences exist to produce an electric field that transverses the tunnel oxide layer 24 (opposite to the direction of the electric field when programming). Therefore, electrons stored in the floating gate 26 will be driven to move toward the channel region 22, and are sucked out to the channel region 22 from the floating gate 26 by Fowler-Nordheim tunneling mechanism. The erase operation is thus completed.
In the prior art, both the program operation and the erase operation which charge or discharge the floating gate utilizes Fowler-Nordheim tunneling mechanism. This method has its native limitation in that the Fowler-Nordheim tunneling behavior of electrons does not happen under the electric field produced by a low potential difference. That means, in order to make this behavior happen, a high potential difference must exist to result in a very slow program speed and erase speed. Furthermore, electrons enter and leave the floating gate 26 through a tunnel window 44, as shown in FIG. 1, in the prior art. Because the tunnel oxide layer 24 inside the tunnel window 44 is very thin, the tunneling behavior of electrons is benefited to improve the performance of the memory device. However, a process problem is encountered.
In the prior art memory cell 14, a buried implant region 46 is respectively formed in portions of the channel region 22 near the source region 16 and the drain region 18, as shown in FIG. 1, before forming the tunnel window 44. The buried implant region 46 is an N-type lightly doped region. The objective of forming the buried implant regions 46 is to lift tunneling efficiency so as to improve program speed and hot electrons injection. Since the tunnel window 44 is within the range of the buried implant region 46, it thus becomes very difficult when aligning the tunnel window 44. In consideration of this problem, the size of the tunnel window 44 cannot be shrunk to avoid the misalignment problem, leading to a barrier to memory cell 14 shrinkage. In some of the prior arts, the methods for forming tiny tunnel windows are taught. However, process steps are complex in these methods to increase processing complexity and cost of products.
Therefore, it is very important to develop a new EEPROM structure. This EEPROM structure should perform program and erase under low operation voltages to improve operation speed. In addition, the need of the tunnel window is eliminated in this EEPROM structure such that the memory cell is shrunk without increasing processing complexity and product costs.